1. Field of the Invention
The invention relates to a method for fabricating transistor, and more particularly, to a method for fabricating metal gate transistor.
2. Description of the Prior Art
In the field of semiconductor fabrication, the use of polysilicon material is diverse. Having a strong resistance for heat, polysilicon materials are commonly used to fabricate gate electrodes for metal-oxide semiconductor transistors. The gate pattern fabricated by polysilicon materials is also used to form self-aligned source/drain regions as polysilicon readily blocks ions from entering the channel region.
However, devices fabricated by polysilicon still have many drawbacks. In contrast to most metal, polysilicon gates are fabricated by semiconductor materials having high resistance, which causes the polysilicon gate to work under a much lower rate than other metal gates. In order to compensate for slightly lowered rate of performance, a significant amount of silicides is applied during the fabrication of polysilicon processes, such that the performance of the device could be increased to an acceptable level.
Gate electrodes fabricated by polysilicon also causes a depletion effect. In most circumstances, the optimum doping concentration for polysilicon is between about 2×2020/cm3 and 3×1020/cm3. As most gate electrodes have a doping concentration of at least 5×1021/cm3, the limited doping concentration of polysilicon gates often results in a depletion region at the interface between the gate and the gate dielectric layer. This depletion region not only thickens the gate dielectric layer, but also lowers the capacitance of the gate and ultimately reduces the driving ability of the device.
In order to resolve this issue, work function metal gates have been developed to replace conventional polysilicon gates. The conventional approach for fabricating metal gates typically forms a dummy gate composed primarily of polysilicon on a substrate, removes the polysilicon material of the dummy gate through dry etching or wet etching, and then deposits a metal into the depleted dummy gate for forming a metal gate.
However, the conventional approach of depleting the polysilicon material from the dummy gate often damages the gate insulating layer underneath. As a result, another thermal oxidation has to be carried out to form another gate insulating layer afterwards. This not only extends the overall fabrication time but also disrupts the distribution of the dopants within the lightly doped drain or source/drain region. Hence, how to effectively resolve the above issue has become an important task.